\chapter{Introduction}
\label{chapter:Introduction}

At its core, a digital computer has at least one \acrfull{cpu}.  A
CPU executes a continuous stream of instructions called a \gls{program}.  
These program instructions are expressed in what is called 
\gls{MachineLanguage}.  Each machine language instruction is a \gls{binary} value.  
In order to provide a method to simplify the management of machine language 
programs a symbolic mapping is provided where a \gls{mnemonic} can be used to 
specify each machine instruction and any of its parameters\ldots\ rather 
than require that programs be expressed as a series of binary values.  
A set of mnemonics, parameters and rules for specifying their use for
the purpose of programming a CPU is called an {\em Assembly Language}.

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\section{The Digital Computer}

There are different types of computers.  A {\em digital} computer is
the type that most people think of when they hear the word {\em computer}.
Other varieties of computers include {\em analog} and {\em quantum}.

A digital computer is one that processes data represented
using numeric values (digits), most commonly expressed in binary
(ones and zeros) form.

This text focuses on digital computing.

A typical digital computer is composed of storage systems (memory, disc 
drives, USB drives, etc.), a CPU (with one or more cores), input peripherals 
(a keyboard and mouse) and output peripherals (display, printer or speakers.)

\subsection{Storage Systems}

Computer storage systems are used to hold the data and instructions
for the CPU.

Types of computer storage can be classified into two categories:
{\em volatile} and {\em non-volatile}.

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\subsubsection{Volatile Storage}
\label{VolatileStorage}

Volatile storage is characterized by the fact that it will lose its
contents (forget) any time that it is powered off.

\index{register}
One type of volatile storage is provided inside the CPU itself in 
small blocks called \glspl{register}.  These registers are used to 
hold individual data values that can be manipulated by the instructions
that are executed by the CPU.  

Another type of volatile storage is {\em main memory}
(sometimes called \acrshort{ram})
Main memory is connected to a computer's CPU and is used to hold
the data and instructions that can not fit into the CPU registers.

Typically, a CPU's registers can hold tens of data values while
the main memory can contain many billions of data values.

To keep track of the data values, each register is assigned a number and
the main memory is broken up into small blocks called \gls{byte}s that 
each assigned a number called an \gls{address} 
(an {\em address} is often referred to as a {\em location.}

A CPU can process data in a register at a speed that can be an order 
of magnitude faster than the rate that it can process (specifically,
transfer data and instructions to and from) the main memory.  

Register storage costs an order of magnitude more to manufacture than
main memory.  While it is desirable to have many registers, the economics 
dictate that the vast majority of volatile computer storage be provided
in its main memory.  As a result, optimizing the copying of data between 
the registers and main memory is a desirable trait of good programs.

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\subsubsection{Non-Volatile Storage}

Non-volatile storage is characterized by the fact that it will {\em NOT} 
lose its contents when it is powered off.

Common types of non-volatile storage are disc drives, 
\acrshort{rom} flash cards and USB 
drives.  Prices can vary widely depending on size and transfer speeds.

It is typical for a computer system's non-volatile storage to operate
more slowly than its main memory.

This text will focus on volatile storage.
%is not particularly concerned with non-volatile storage. 

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\subsection{CPU}
\index{CPU}

\enote{Add a block diagram of the CPU components described here.}
The \acrshort{cpu} is a collection of registers and circuitry designed to
manipulate the register data and to exchange data and instructions with the 
main memory.  The instructions that are read from the main memory tell 
the CPU to perform various mathematical and logical operations on the data 
in its registers and where to save the results of those operations.

\subsubsection{Execution Unit}

The part of a CPU that coordinates all aspects of the operations of each 
instruction is called the {\em execution unit.}  It is what performs the transfers 
of instructions and data between the CPU and the main memory and tells the 
registers when they are supposed to either store or recall data being transferred.  
The execution unit also controls the ALU (Arithmetic and Logic Unit).

\subsubsection{Arithmetic and Logic Unit}
\index{ALU}

When an instruction manipulates data by performing things like an {\em addition},
{\em subtraction}, {\em comparison} or other similar operations , the ALU is what
will calculate the sum, difference, and so on\ldots\ under the control of the 
execution unit.



\subsubsection{Registers}
\index{register}

In the RV32 CPU there are 31 general purpose registers that each contain 32 \gls{bit}s 
(where each bit is one \gls{binary} digit value of one or zero) and a number 
of special-purpose registers.
Each of the general purpose registers is given a name such as \reg{x1}, \reg{x2},
\ldots\ on up to \reg{x31} ({\em general purpose} refers to the fact that the 
{\em CPU itself} does not prescribe any particular function to any of these registers.)
Two important special-purpose registers are \reg{x0} and \reg{pc}.

Register \reg{x0} will always represent the value zero or logical {\em false}  
no matter what.  If any instruction tries to change the value in \reg{x0} the 
operation will fail.  The need for {\em zero} is so common that, other than the 
fact that it is hard-wired to zero, the \reg{x0} register is made available as 
if it were otherwise a general purpose register.%
\footnote{Having a special 
{\em zero} register allows the total set of instructions that the CPU can execute 
to be simplified.  Thus reducing its complexity, power consumption and cost.} 

The \reg{pc} register is called the {\em program counter}.  The CPU uses it to
remember the memory address where its program instructions are located.

\enote{Say something about XLEN?}%
The number of bits in each register is defined by the \acrfull{isa}.

\subsubsection{Harts}
\index{hart}

Analogous to a {\em core} in other types of CPUs, a {\em \acrshort{hart}} 
(hardware \gls{thread}) in a RISC-V CPU refers to the collection of 32 registers,
instruction execution unit and ALU.\cite[p.~20]{rvismv1v22:2017}

When more than one hart is present in a CPU, a different stream of instructions can 
be executed on each hart all at the same time.
Programs that are written to take advantage of this are called {\em multithreaded}.

This text will primarily focus on CPUs that have only one hart.

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\subsection{Peripherals}

A {\em peripheral} is a device that is not a CPU or main memory.  They are 
typically used to transfer information/data into and out of the 
main memory.

This text is not concerned with the peripherals of a computer
system other than in sections where instructions are discussed with the
purpose of addressing the needs of a peripheral device.  Such
instructions are used to initiate, execute and/or synchronize data transfers.


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\section{Instruction Set Architecture}
\index{ISA}

The catalog of rules that describes the details of the instructions 
and features that a given CPU provides is called an \acrfull{isa}.

An ISA is typically expressed in terms of the specific meaning of
each binary instruction that a CPU can recognize and how it will
process each one.

The RISC-V ISA is defined as a set of modules.  The purpose of
dividing the ISA into modules is to allow an implementer to select which 
features to incorporate into a CPU design.\cite[p.~4]{rvismv1v22:2017}

Any given RISC-V implementation must provide one of the {\em base}
modules and zero or more of the {\em extension} modules.\cite[p.~4]{rvismv1v22:2017}

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\subsection{RV Base Modules}
\index{RV32I}

The base modules are RV32I (32-bit general purpose), 
RV32E (32-bit embedded), RV64I (64-bit general purpose) 
and RV128I (128-bit general purpose).\cite[p.~4]{rvismv1v22:2017}

These base modules provide the minimal functional set of integer operations
needed to execute a useful application.  The differing bit-widths address
the needs of different main-memory sizes.

This text primarily focuses on the RV32I base module and how to program it.


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\subsection{Extension Modules}

RISC-V extension modules may be included by an implementer interested
in optimizing a design for one or more purposes.\cite[p.~4]{rvismv1v22:2017}

\index{RV32M}%
\index{RV32A}%
\index{RV32F}%
\index{RV32D}%
\index{RV32Q}%
\index{RV32C}%
Available extension modules include M (integer math), A (atomic),
F (32-bit floating point), D (64-bit floating point), 
Q (128-bit floating point), C (compressed size instructions) and others.

\index{RV32G}%
The extension name {\em G} is used to represent the combined set of IMAFD
extensions as it is expected to be a common combination.




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\section{How the CPU Executes a Program}

The process of executing a program is continuous repeats of a series of
\index{instruction cycle}{\em instruction cycles} that are each comprised
of a {\em fetch}, {\em decode} and {\em execute} phase.
 
The current status of a CPU hart is entirely embodied in the data values that
are stored in its registers at any moment in time.  Of particular interest
to an executing program is the \reg{pc} register.  The \reg{pc} contains
the memory address containing the instruction that the CPU is currently 
executing.\footnote{In the RISC-V ISA the \reg{pc} register points to the 
{\em current} instruction where in most other designs, the \reg{pc}
register points to the {\em next} instruction.}

For this to work, the instructions to be executed must have been previously 
stored in adjacent main memory locations and the address of the first instruction 
placed into the \reg{pc} register.


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\subsection{Instruction Fetch}
\index{instruction fetch}

In order to {\em fetch} an instruction from the main memory the CPU
will update the address in the \reg{pc} register and then request that
the main memory return the value of the data stored at that address.
\footnote{RV32I instructions are more than one byte in size, but 
this general description is suitable for now.}

%must have a method to identify which instruction should be fetched and
%a method to fetch it. 

%Given that the main memory is broken up and that each of its bytes is 
%assigned an address, the \reg{pc} is used to hold the address of the
%location where the next instruction to execute is located.

%Given an instruction address, the CPU can request that the main memory 
%locate and return the value of the data stored there using what is called 
%a {\em memory read} operation and then the CPU can treat that {\em fetched}
%value as an instruction and execute it.


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\subsection{Instruction Decode}
\index{instruction decode}

Once an instruction has been fetched, it must be inspected to determine what
operation(s) are to be performed.  This means inspecting the portions of the 
instruction that dictate which registers are involved and what that, if 
anything, ALU should do.

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\subsection{Instruction Execute}
\index{instruction execute}

Typical instructions do things like add a number to the value
currently stored in one of the registers or store the contents of a
register into the main memory at some given address.

Part of every instruction is a notion of what should be done next.

Most of the time an instruction will complete by indicating that
the CPU should proceed to fetch and execute the instruction at the next
larger main memory address.  In these cases the \reg{pc} is incremented
to point to the memory address after the current instruction.

Any parameters that an instruction requires must either be part of 
the instruction itself or read from (or stored into) one or more of the 
general purpose registers.

Some instructions can specify that the CPU proceed to execute an
instruction at an address other than the one that follows itself.
This class of instructions have names like {\em jump} and {\em branch}
and are available in a variety of different styles.

The RISC-V ISA uses the word {\em jump} to refer to an {\em unconditional}
change in the sequential processing of instructions and the word
{\em branch} to refer to a {\em conditional} change.

Conditional branch instructions can be used to tell the CPU to 
do things like:

\begin{quote}
If the value in x8 is currently less than the value in x24 then
proceed to the instruction at the next main memory address, otherwise
branch to an instruction at a different address.
\end{quote}

This type of instruction can therefore result in one of two different 
actions pending the result of the 
comparison.\footnote{This is the fundamental method used by a CPU 
to make decisions.}

Once the instruction execution phase has completed, the next instruction 
cycle will be performed using the new value in the \reg{pc} register.
